The present invention relates to ferroelectric memories and methods for manufacturing the same.
Ferroelectric memories (FRAMs: ferroelectric random access memories) provided with a ferroelectric layer as a dielectric layer of a capacitor are being developed in recent years. Ferroelectric has a characteristic in that polarization occurring upon application of a voltage remains even after the voltage application is stopped, and the remanence is retained for several ten years. Also, ferroelectric has a characteristic in that its polarization occur in a very short time of several ns, and the orientation of polarization changes by application of an electric field. Accordingly, a ferroelectric memory is a nonvolatile memory having a high data retention characteristic, such that write and readout operations to capacitors can be executed at high speed.
As a ferroelectric memory structure, a “stacked type” in which a source/drain region of a transistor and a lower electrode of a capacitor are directly connected to each other by a contact plug is known. A stacked type ferroelectric memory is effective in view of the fact that its cell area can be made small. In a conventional stacked type ferroelectric memory, contact plugs for connection with plate lines are formed on upper electrodes of capacitors. Tungsten that is low in resistance is suitable as a material for these contact plugs. A CVD method, in which the reaction is caused with tungsten fluoride and hydrogen as materials, is generally practiced as a method for forming tungsten plugs.
Also, PZT (Pb (Zrx Ti(1-x))O3), SBT (SrBi2 Ta2 O9) and the like are known as materials of ferroelectric layers. However, these materials would likely be reduced by hydrogen, and their polarization characteristics lower when they are reduced. When the polarization characteristics of ferroelectric layers lower, the characteristics of ferroelectric memories deteriorate. Therefore it is necessary to prevent hydrogen from entering ferroelectric layers. For this reason, conventionally, it has been proposed to cover side surfaces and upper surfaces (upper surfaces of upper electrodes) of ferroelectric capacitors by a dielectric hydrogen barrier layer.
However, the step of forming tungsten plugs on the upper electrodes of the ferroelectric capacitors needs to be conducted in a state in which contact holes are opened in the hydrogen barrier layer provided on the upper surfaces of the upper electrodes, and the upper electrodes are therefore exposed. For this reason, even when the side surfaces and upper surfaces (upper surface of each upper electrode) of the ferroelectric capacitors are covered by a dielectric hydrogen barrier layer, the upper electrodes are exposed to hydrogen in this step, and penetration of hydrogen to the ferroelectric layers cannot be securely prevented.
Patent Document 1 below proposes a method to prevent penetration of hydrogen in ferroelectric layers of a stacked type ferroelectric memory, wherein a conductive hydrogen barrier layer is provided between a lower electrode of a ferroelectric capacitor and a contact plug, an upper electrode of each of plural capacitors (arranged in a word line direction) that are connected to a common plate line and the ferroelectric layer are commonly formed (patterning is not conducted after formation of a thin film), a gap between adjacent ones of the lower electrodes is embedded with a dielectric hydrogen barrier layer, and a common dielectric hydrogen barrier layer is also formed on the upper electrode.
[Patent Document 1] Japanese Laid-open Patent Application 2003-174145
However, in the method described in the above Patent Document 1, because upper electrodes of plural capacitors (arranged in a word line direction) that are connected to a common plate line and ferroelectric layers are commonly formed, there is a problem in that parasitic capacitance is generated between the plural ferroelectric capacitors.
It is an object of the present invention to securely prevent penetration of hydrogen into a ferroelectric layer of a ferroelectric memory by a method in which parasitic capacitance is difficult to be generated among plural ferroelectric capacitors, compared to the method described in the above Patent Document 1.